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DATA SHEET
PCF8535 65 x 133 pixel matrix driver
Objective specification File under Integrated Circuits, IC12 1999 Aug 24
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
CONTENTS 1 2 3 4 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM Block diagram functions Oscillator Power-on reset I2C-bus controller Input filters Display data RAM Timing generator Address counter Display address counter PINNING Pin functions R0 to R64 C0 to C132 VSS1 and VSS2 VDD1 to VDD3 VLCDOUT VLCDIN VLCDSENSE SDA SDAOUT SCL SA0 and SA1 OSC RES T1, T2, T3, T4 and T5 FUNCTIONAL DESCRIPTION Reset Power-down LCD voltage selector Oscillator Timing Column driver outputs Row driver outputs Drive waveforms Set multiplex rate 7.10 7.10.1 7.11 7.11.1 7.12 7.12.1 7.13 7.13.1 7.14 7.14.1 7.15 7.15.1 7.15.2 7.16 7.16.1 7.16.2 7.16.3 7.16.4 7.16.5 7.16.6 7.17 7.17.1 7.17.2 8 9 10 11 12 13 14 15 16 17 18 19 20
PCF8535
Bias system Set bias system Temperature measurement Temperature read back Temperature compensation Temperature coefficients VOP Set VOP value Voltage multiplier control S[1:0] Addressing Input addressing Output addressing Instruction set RAM read/write command page Function and RAM command page Display setting command page HV-gen command page Special feature command page Instruction set I2C-bus interface Characteristics of the I2C-bus I2C-bus protocol LIMITING VALUES (PROVISIONAL) HANDLING DC CHARACTERISTICS AC CHARACTERISTICS RESET TIMING APPLICATION INFORMATION BONDING PAD LOCATIONS DEVICE PROTECTION DIAGRAM TRAY INFORMATION DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS BARE DIE DISCLAIMER
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
1 FEATURES
PCF8535
* Single-chip LCD controller/driver * 65 row, 133 column outputs * Display data RAM 65 x 133 bits * 133 icons (last row is used for icons) * Fast mode I2C-bus interface (400 kbits/s) * Software selectable multiplex rates: 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65 * On-chip: - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible) - Generation of VLCD. * CMOS compatible inputs * Software selectable bias configuration * Logic supply voltage range VDD1 to VSS1 4.5 to 5.5 V * Supply voltage range for high voltage part VDD2 and VDD3 to VSS2 and VSS3 4.5 to 5.5 V * Display supply voltage range VLCD to VSS: - Mux rate 1 : 65: 8 to 16 V. * Low power consumption, suitable for battery operated systems * Internal Power-on reset and/or external reset * Temperature read back available * Manufactured in N-well silicon gate CMOS process. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8535U - DESCRIPTION chip with bumps in tray VERSION - 2 APPLICATIONS
* Automotive information systems * Telecommunication systems * Point-of-sale terminals * Instrumentation. 3 GENERAL DESCRIPTION
The PCF8535 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65. Furthermore, it can drive up to 133 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8535 is compatible with most microcontrollers and communicates via an industry standard two-line bidirectional I2C-bus serial interface. All inputs are CMOS compatible.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
5 BLOCK DIAGRAM
PCF8535
handbook, full pagewidth
R0 to R64
C0 to C132
VDD1
VDD2
VDD3
65 VSS1 VSS2 T4, T5 T1, T2, T3 ROW DRIVERS
133 COLUMN DRIVERS POWER-ON RESET
PCF8535
INTERNAL RESET
RES
DATA LATCHES VLCDIN BIAS VOLTAGE GENERATOR MATRIX LATCHES
OSCILLATOR
OSC
TIMING GENERATOR DISPLAY DATA RAM VLCD GENERATOR MATRIX DATA RAM DISPLAY ADDRESS COUNTER
VLCDSENSE VLCDOUT
SCL SDA SDAOUT INPUT FILTERS
I2C-BUS CONTROL
COMMAND DECODER
ADDRESS COUNTER
MGS669
SA1
SA0
Fig.1 Block diagram.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
5.1 5.1.1 Block diagram functions OSCILLATOR 5.1.5 DISPLAY DATA RAM
PCF8535
The on-chip oscillator provides the display clock for the system; it requires no external components. Alternatively, an external display clock may be provided via the OSC input. The OSC input must be connected to VDD1 or VSS1 when not in use. During power-down additional current saving can be made if the external clock is disabled. 5.1.2 POWER-ON RESET
The PCF8535 contains a 65 x 133 bit static RAM which stores the display data. The RAM is divided into 9 banks of 133 bytes. The last bank is used for icon data and is only one bit deep. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and the column output number. 5.1.6 TIMING GENERATOR
The on-chip Power-on reset initializes the chip after power-on or power failure. 5.1.3 I2C-BUS CONTROLLER
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data bus. 5.1.7 ADDRESS COUNTER
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display data bytes. It performs the conversion of the data input (serial-to-parallel). The PCF8535 acts as an I2C-bus slave and therefore cannot initiate bus communication. 5.1.4 INPUT FILTERS
The Address Counter (AC) sends addresses to the Display Data RAM (DDRAM) for writing. 5.1.8 DISPLAY ADDRESS COUNTER
Input filters are provided to enhance noise immunity in electrically adverse environments; RC low-pass filters are provided on the SDA, SCL and RES lines.
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on or off, normal or inverse video) is set via the I2C-bus.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
6 PINNING SYMBOL 1 2 R0 to R15 C0 to C132 R47 to R33 3 to 18 19 to 151 152 to 166 167 168 R48 to R64 169 to 185 186 187 to 189 OSC VLCDIN VLCDOUT VLCDSENSE RES T3 T2 T1 VDD2 VDD3 VDD1 SDA SDAOUT SA1 SA0 VSS2 VSS1 T5 T4 SCL R32 to R16 6.1 6.1.1 Pin functions R0 TO R64 190 191 to 196 197 to 203 204 205 and 206 207 208 209 210 211 to 218 219 to 222 223 to 228 229 230 and 231 232 233 234 235 to 242 243 to 250 251 252 253 254 and 255 256 257 to 273 PAD dummy pad bump/alignment mark 1 LCD row driver outputs LCD column driver outputs LCD row driver outputs bump/alignment mark 2 dummy pad LCD row driver outputs; R64 is icon row bump/alignment mark 3 dummy pad oscillator LCD supply voltage voltage multiplier output voltage multiplier regulation input (VLCD) dummy pad external reset input (active LOW) test output 3 test output 2 test output 1 supply voltage 2 supply voltage 3 supply voltage 1 dummy pad I2C-bus serial data inputs I2C-bus serial data output I2C-bus slave address input I2C-bus slave address input ground 2 ground 1 test input 5 test input 4 dummy pad I2C-bus serial clock inputs bump/alignment mark 4 LCD row driver outputs DESCRIPTION
PCF8535
These pads output the display row signals.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
6.1.2 C0 TO C132
PCF8535
and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8535 will not be able to create a valid logic 0 level. By splitting the SDA input from the SDAOUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required or where read back is required, it is necessary to minimize the track resistance from the SDAOUT pad to the system SDA line to guarantee a valid LOW level. 6.1.10 SCL
These pads output the display column signals. 6.1.3 VSS1 AND VSS2
VSS1 and VSS2 must be connected together. 6.1.4 VDD1 TO VDD3
VDD1 is the logic supply. VDD2 and VDD3 are for the voltage multiplier. For split power supplies VDD2 and VDD3 must be connected together. If only one supply voltage is available, all three supplies must be connected together. 6.1.5 VLCDOUT
I2C-bus serial clock input. 6.1.11 SA0 AND SA1
If, in the application, an external VLCD is used, VLCDOUT must be left open-circuit; otherwise (if the internal voltage multiplier is enabled) the chip may be damaged. VLCDOUT should not be driven when VDD1 is below its minimum allowed value otherwise a low impedance path between VLCDOUT and VSS1 will exist. 6.1.6 VLCDIN
Least significant bits of the I2C-bus slave address. Table 1 Slave address; see note 1 MODE write read 0 and 1 1 and 0 1 and 1 write read write read write read Note 1. The slave address is a concatination of the following bits {01111, SA1, SA0 and R/W}. 6.1.12 OSC SLAVE ADDRESS 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH
SA1 AND SA0 0 and 0
This is the VLCD supply for when an external VLCD is used. If the internal VLCD generator is used, then VLCDOUT and VLCDIN must be connected together. VLCDIN should not be driven when VDD1 is below its minimum allowed value, otherwise a low impedance path between VLCDIN and VSS1 will exist. 6.1.7 VLCDSENSE
This is the input to the internal voltage multiplier regulator. It must be connected to VLCDOUT when the internal voltage generator is used otherwise it may be left open-circuit. VLCDSENCE should not be driven when VDD1 is below its minimum allowed value, otherwise a low impedance path between VLCDSENCE and VSS1 will exist. 6.1.8 SDA
If the on-chip oscillator is used this input must be connected to VDD1 or VSS1. 6.1.13 RES
I2C-bus serial data input. 6.1.9 SDAOUT
SDAOUT is the serial data acknowledge for the I2C-bus. By connecting SDAOUT to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor 1999 Aug 24 7
External reset pad: when this pad is LOW the chip will be reset; see Section 7.1. If an external reset is not required, this pad must be tied to VDD1. Timing for the RES pad is given in Chapter 12. 6.1.14 T1, T2, T3, T4 AND T5
In applications T4 and T5 must be connected to VSS. T1, T2 and T3 are to be left open-circuit.
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7 FUNCTIONAL DESCRIPTION
PCF8535
The PCF8535 is a low power LCD driver designed to interface with microprocessors/microcontrollers and a wide variety of LCDs. The host microprocessor/microcontroller and the PCF8535 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD.
handbook, full pagewidth
VLCD
VDD1 to VDD3 VDD1, VDD3 VDD2 VDD(I2C) 133 column drivers 65 row drivers Rpu Rpu HOST MICROPROCESSOR/ MICROCONTROLLER VSS1 VSS2
PCF8535
LCD PANEL
VSS RES SA0 SA1 SCL SDA VSS1, VSS2
MGS670
Fig.2 Typical system configuration.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.1 Reset 7.3 LCD voltage selector
PCF8535
The PCF8535 has two reset modes; internal Power-on reset or external reset. Reset initiated from either the RES pad or the internal Power-on reset block will initialize the chip to the following starting condition: * Power-down mode (PD = 1) * Horizontal addressing (V = 0); no mirror X or Y (MX = 0 and MY = 0) * Display blank (D = 0 and E = 0) * Address counter X[6:0] = 0, Y[2:0] = 0 and XM0 = 0 * Bias system BS[2:0] = 0 * Multiplex rate M[2:0] = 0 (Mux rate 1 : 17) * Temperature control mode TC[2:0] = 0 * HV-gen control, HVE = 0 the HV generator is switched off, PRS = 0 and S[1:0] = 00 * VLCDOUT is equal to 0 V * RAM data is unchanged (Note: RAM data is undefined after power-up) * All row and column outputs are set to VSS (display off) * TRS and BRS are set to zero * Direct mode is disabled (DM = 0) * Internal oscillator is selected, but not running (EC = 0) * Bias current set to low current mode (IB = 0). 7.2 Power-down
The practical value for VOP is determined by equating Voff(rms) with defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. 7.4 Oscillator
The internal logic operation and the multi-level drive signals of the PCF8535 are clocked by the built-in RC oscillator. No external components are required. 7.5 Timing
The timing of the PCF8535 organizes the internal data flow of the device. The timing also generates the LCD frame frequency which is derived from the clock frequency generated in the internal clock generator. 7.6 Column driver outputs
The LCD drive section includes 133 column outputs (C0 to C132) which should be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. When less than 133 columns are required the unused column outputs should be left open-circuit. 7.7 Row driver outputs
During power-down all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system) and all LCD outputs are internally connected to VSS. The serial bus function remains active.
The LCD drive section includes 65 row outputs (R0 to R64) which should be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If lower Mux rates or less than 65 rows are required, the unused outputs should be left open-circuit.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.8 Drive waveforms
PCF8535
frame n
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
frame n + 1 Vstate1(t) Vstate2 (t)
ROW 0 R0 (t)
ROW 1 R1 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD
Vstate1(t)
Vstate2 (t)
0 1 2 3 4 5 6 7 8...
... 64 0 1 2 3 4 5 6 7 8...
... 64
MGS671
Vstate1(t) = C1(t) - R0(t). Vstate2(t) = C1(t) - R1(t).
Fig.3 Typical LCD driver waveforms.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.9 Set multiplex rate
PCF8535
The PCF8535 can be used to drive displays of varying sizes. The multiplex mode selected controls which rows are used. In all cases, the last row is always driven and is intended for icons. If Top Row Swap (TRS) is at logic 1 then the icon row will be output on pad R48. M[2:0] selects the multiplex rate (see Table 2). Table 2 Multiplex rates M[1] 0 0 1 1 0 101 - 111 7.10 7.10.1 Bias system SET BIAS SYSTEM M[0] 0 1 0 1 0 MULTIPLEX RATE 1 : 17 1 : 26 1 : 34 1 : 49 1 : 65 do not use ACTIVE ROWS R0 to R15 and R64 R0 to R24 and R64 R0 to R32 and R64 R0 to R47 and R64 R0 to R64 -
M[2] 0 0 0 0 1
The bias voltage levels are set in the ratio of R - R - nR - R - R. Different multiplex rates require different factors n. This is programmed by BS[2:0]. For optimum bias values, n can be calculated from: n = Mux rate - 3
Changing the bias system from the optimum will have a consequence on the contrast and viewing angle. One reason to come away from the optimum would be to reduce the required VOP. A compromise between contrast and VOP must be found for any particular application. Table 3 Programming the required bias system BS[1] 0 0 1 1 0 0 1 1 BS[0] 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0 BIAS MODE
1/ 11 1/ 10 1/ 9 1/ 8 1/ 7 1/ 6 1/ 5 1/ 4
BS[2] 0 0 0 0 1 1 1 1
TYPICAL MUX RATES 1 : 100 1 : 80 1 : 65 1 : 49 1 : 33 1 : 26 1 : 17 1:9
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
Table 4 Example of LCD bias voltage for 1/7bias, n = 3 BIAS VOLTAGE FOR 1/7BIAS VLCD
6/ 7 5/ 7 2/ 7 1/ 7
PCF8535
For calibrating the temperature read-out a measurement must be taken at a defined temperature. The offset between the ideal read-out and the actual result has to be stored into a non-volatile register (e.g. EEPROM); Offset = TR ideal - TR meas (2) where TRmeas is the actual temperature read-out of the PCF8535. The calibrated temperature read-out can be calculated for each measurement as follows: TR cal = TR meas + Offset (3) The accuracy after the calibration is 6.7% (plus 1 lsb) of the difference between the current temperature and the calibration temperature. For this reason a calibration at or near the most sensitive temperature for the display is recommended. E.g. for a calibration at 25 C with the current temperature at -20 C, the absolute error may be calculated as: Absolute error = 0.067 x (25 C - -20 C) = 3 C + 1 lsb = 4.17 C. 7.12 7.12.1 Temperature compensation TEMPERATURE COEFFICIENTS
SYMBOL V1 V2 V3 V4 V5 V6 7.11 7.11.1
x VLCD x VLCD x VLCD x VLCD VSS
Temperature measurement TEMPERATURE READ BACK
The PCF8535 has an in-built temperature sensor. For power saving, the sensor should only be enabled when a measurement is required. It will not operate in power-down mode. The temperature read back requires a clock to operate. Normally the internal clock is used but, if the device is operating from an external clock, then this must be present for the measurement to work. VDD2 and VDD3 must also be applied. A measurement is initialized by setting the SM bit. Once started the SM bit will be automatically cleared. An internal oscillator will be initialized and allowed to warm-up for approximately 2 frame periods. After this the measurement starts and lasts for a maximum of 2 frame periods. Temperature data is returned via a status register. During the measurement the register will contain zero. Once the measurement is completed the register will be updated with the current temperature (non zero value). Because the I2C-bus interface is asynchronous to the temperature measurement, read back prior to the end of the measurement is not guaranteed. If this mode is required the register should be read twice to validate the data. The ideal temperature read-out can be calculated as follows; 1 TR ideal = 128 + ( T - 27 C ) x -c where T is the on-chip temperature in C and c is the conversion constant; c = 1.17 C/lsb. To improve the accuracy of the temperature measurement a calibration is recommended during the assembly of the final product.
Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage, V must be increased at lower temperatures to maintain optimum contrast. Figure 4 shows VLCD as a function of temperature for a typical high multiplex rate liquid. In the PCF8535 the temperature coefficient of VLCD can be selected from 8 values by setting bits TC[2:0], see Table 5.
(1)
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, halfpage
MGS473
VLCD
0 C
T
Fig.4 VLCD as function of liquid crystal temperature (typical values).
Table 5 TC[2] 0 0 0 0 1 1 1 1 7.13 7.13.1
Selectable temperature coefficients TC[1] 0 0 1 1 0 0 1 1 TC[0] 0 1 0 1 0 1 0 1 TC VALUE 0 -0.44 x -1.45 x 10-3 10-3 -1.10 x 10-3 -1.91 x 10-3 -2.15 x 10-3 -2.32 x -2.74 x 10-3 10-3 UNIT 1/C 1/C 1/C 1/C 1/C 1/C 1/C 1/C
The low range offers programming from 4.5 to 10.215 V, with the high range from 10.215 to 15.93 V at the cut point temperature, Tcut. Care must be taken, when using temperature coefficients, that the programmed voltage does not exceed the maximum allowed VLCD voltage, see Chapter 10. For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate. For a Mux rate of 1 : 65, the optimum operating voltage of the liquid can be calculated as: 1 + 65 V LCD = -------------------------------------- x V th = 6.85 x V th 1 2 x 1 - ---------- 65 where Vth is the threshold voltage of the liquid crystal material used. Table 6 Values for parameters of the HV generator programming BITS PRS = 0 PRS = 1 b Tcut VALUE 4.5 10.215 0.045 27 UNIT V V V C (6)
VOP SET VOP VALUE
The voltage at the reference temperature can be calculated as: [VLCD (T = Tcut)] V LCD = ( a + V OP x b )
( Tcut )
(4)
The operating voltage, VOP, can be set by software. The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at the reference temperature (Tcut): (5) V LCD = ( a + V OP x b ) x ( 1 + ( ( T - T cut ) x TC ) ) The values for Tcut, a and b are given in Table 6. The maximum voltage that can be generated is dependent on the voltage VDD2 and the display load current. Two overlapping VOP ranges are selectable via the command page "Hv-gen control", see Fig.5.
SYMBOL a
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, full pagewidth
VLCD
b
a
00
01
02
03
04
05 LOW
06
. . . 5F
6F
7F
00
01
02
03
04
05 HIGH
06
. . . 5F
6F
7F
MGS472
VOP[6:0] programming (00H to 7FH, programming range LOW and HIGH).
Fig.5 VOP programming of PCF8535.
7.14 7.14.1
Voltage multiplier control S[1:0]
Table 7 S[1] 0 0 1 1
HV generator multiplication factor S[0] 0 1 0 1 MULTIPLICATION FACTOR 2 x VDD2 3 x VDD2 4 x VDD2 5 x VDD2
The PCF8535 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 x VDD2. Other voltage multiplier factors are set via the HV-gen command page. Before switching on the charge pump, the charge pump has to be pre-charged using the following sequence. A starting state of HVE = 0, DOF = 0, PD = 1 and DM = 0 is assumed. A small delay between steps is indicated. The recommended wait period is 20 s per 100 nF of capacitance on VLCD1. 1. Set DM = 1 and PD = 0 2. Delay 3. Set the multiplication factor to 2 by setting S[1:0] = 00 4. Set the required VOP and PRS. 5. Set HVE = 1 to switch-on the charge pump with a multiplication factor of 2 6. Delay 7. Increase the number of stages, one at a time, with a delay between each until the required level is achieved. 1999 Aug 24 14
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15 Addressing
PCF8535
The display RAM has a matrix of 65 x 133 bits. The columns are addressed by a combination of the X address pointer and the X-RAM page pointer, whilst the rows addressed in groups of 8 by the Y address pointer. The X address pointer has a range of 0 to 127 (7FH). Its range can be extended by the X-RAM page pointer, XM0. The Y address pointer has a range of 0 to 8 (08H). The PCF8535 is limited to 133 columns by 65 rows, addressing the RAM outside of this area is not allowed.
Addressing of the RAM can be split into two parts; input addressing and output addressing. Input addressing is concerned with writing data into the RAM. Output addressing is almost entirely automatic and taken care of by the device, however, it is possible to affect the output mode. 7.15.1 INPUT ADDRESSING
Data is down loaded byte wise into the RAM matrix of the PCF8535 as indicated in Figs 6 to 10. Table 8 Effect of X-RAM page pointer X-RAM PAGE POINTER XM0 0 0 0 : 0 0 0 1 1 : 1 ADDRESSED COLUMN MX = 0 C0 C1 C2 : C125 C126 C127 C128 C129 : C132 ADDRESSED COLUMN MX = 1 C132 C131 C130 : C7 C6 C5 C4 C3 : C0
X ADDRESS POINTER 0 1 2 : 125 126 127 0 1 : 4
Banks 1 to 7 use the entire byte MSB handbook, full pagewidth XM0 = 0 XM0 = 1 0 1 LSB 2 3 4 5 6 7 icon data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 119 120 121 122 123 124 125 126 127 0 1 2 3 4
MSB
8
LSB
.. ..
.. ..
X address
MGS673
Fig.6 RAM format, input addressing.
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Y address
Bank 8 is only 1 bit deep and uses the MSB
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
MSB Data byte in location X = 0, Y = 0, MX0 = 0 (MX = 0, MY = 0)
bank 0 top of LCD R0
LSB bank 1 R8
bank 2 R16
LCD
bank 3
R24
MSB Data byte in location Y = 7, X = 0, MX0 = 0 (MX = 0, MY = 0)
bank 7
R56
LSB bank 8
R64
MGS674
Fig.7 DDRAM to display mapping.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
Two automated addressing modes are available; vertical addressing (V = 1) and horizontal addressing (V = 0). These modes change the way in which the auto-incrementing of the address pointers is handled and are independent of multiplex rate. The auto-incrementing works in a way so as to aid filling of the entire RAM. It is not a prerequisite of operation that the entire RAM is filled; in lower multiplex modes not all of the RAM will be needed. For these multiplex rates, use of horizontal addressing mode (V = 0) is recommended. Addressing the icon row is a special case as these RAM locations are not automatically accessed. These locations must be explicitly addressed by setting the Y address pointer to 8. The Y address pointer does not auto-increment when the X address over or underflows, it stays set to 8. Writing icon data is independent of the vertical and horizontal addressing mode, but is effected by the mirror X bit as described in Sections 7.15.1.2 and 7.15.1.3.
PCF8535
The addressing modes may be further modified by the mirror X bit MX. This bit causes the data to be written into the RAM from right to left instead of the normal left to right. This effectively flips the display about the Y axis. The MX bit affects the mode of writing into the RAM, changing the MX bit after RAM data is written will not flip the display.
7.15.1.1
Vertical addressing: non-mirrored; V = 1 and MX = 0
In the vertical addressing mode data is written top to bottom and left to right. Here, the Y counter will auto-increment from 0 to 7 and then wrap around to 0 (see Fig.8). On each wrap over, the X counter will increment to address the next column. When the X counter wraps over from 127 to 0, the XM0 bit will be set. The last address accessible is Y = 7, X = 4 and XM0 = 1; after this access the counter will wrap around to Y = 0, X = 0 and XM0 = 0.
handbook, full pagewidth
byte number
0 8 16 24
XM0 = 0
XM0 = 1
1015 1014 1013 1012 .... 1023 1022 1021 1020 1019 1018 1017 1016 1031 1030 1029 1028 1027 1026 1025 1024 .... 1035 1034 1033 1032
0 1 2
....
....
3 11 19
2 10 18 26
1 9 17 25
3 4 5 6 7 8 Y address
MGS675
byte order for icon data
icon data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
X address
Fig.8 Sequence of writing data bytes into the RAM with normal vertical addressing (V = 1 and MX = 0).
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119 120 121 122 123 124 125 126 127 0 1 2 3 4
.. ..
.. ..
119 120 121 122 123 124 125 126 127 128 129 130 131 132
12 13 14 15 16 17 18 19 20 21 22 23 24
0 1 2
1063 1062 1061 1060
7 15 23
6 14 22
5 13 21
4 12 20
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15.1.2 Vertical addressing: mirrored; V = 1 and MX = 1
PCF8535
It is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. In the mirrored vertical addressing mode the Y counter will auto-increment from 0 to 7 and then wrap around to 0 (see Fig.9). On each wrap-over, the X counter will decrement to address the preceding column. The XM0 bit will be automatically toggled each time the X address counter wraps over from 0. The last address accessible is Y = 7, X = 0 and XM0 = 0; after this access the counter will wrap around to Y = 0, X = 4 and XM0 = 1.
handbook, full pagewidth
byte number
1063 1062 1061 1060 1059 1058 1057 1056 1055 1054 1053 1052 ....
XM0 = 0
XM0 = 1
48 40 32
0 1 2 3 4 5 6 7 8 Y address
49 41 33
....
50 42 34
....
43 35
44 36
....
45 37
46 38 30
byte order for icon data
47 39 31
132 131 130
120 119 118 117 116 115 114 113 112 111 110 109 108
icon data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
X address
MGS676
Fig.9 Sequence of writing data bytes into the RAM with mirrored vertical addressing (V = 1 and MX = 1).
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119 120 121 122 123 124 125 126 127 0 1 2 3 4
.. ..
.. ..
13 12 11 10 9 8 7 6 5 4 3 2 1 0
7
6
5
4
3
10 2
9 1
8 0
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15.1.3 Horizontal addressing: non-mirrored; V = 0 and MX = 0
PCF8535
In horizontal addressing mode data is written from left to right and top to bottom. Here, the X counter will auto-increment from 0 to 127, set the XM0, then count 0 to 4 before wrapping around to 0 and clearing the XM0 bit (see Fig.10). On each wrap-over, the Y counter will increment. The last address accessible is Y = 7, X = 4 and XM0 = 1; after this access the counter will wrap around to Y = 0, X = 0 and XM0 = 0.
handbook, full pagewidth
byte number
XM0 = 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
XM0 = 1
119 120 121 122 123 124 125 126 127 128 129 130 131 132
0 1 2 3 4 5 Y address
MGS677
133 134 135 136
....
924 925 926 927 928 929 930
....
6 7 8
icon data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
X address
Fig.10 Sequence of writing data bytes into the RAM with normal horizontal addressing (V = 0 and MX = 0).
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119 120 121 122 123 124 125 126 127 0 1 2 3 4
.. ..
.. ..
119 120 121 122 123 124 125 126 127 128 129 130 131 132
12 13 14 15 16 17 18 19 20 21 22 23 24
0 1 2
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955
byte order for icon data
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15.1.4 Horizontal addressing: mirrored; V = 0 and MX = 1
PCF8535
It is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. In the mirrored horizontal addressing mode the X counter will auto-decrement from 4 to 0, clear the XM0, then count 127 to 0 before wrapping around to 4 and setting the XM0 bit (see Fig.10). On each wrap-over, the Y counter will increment. The last address accessible is Y = 7, X = 0 and XM0 = 0; after this access the counter will wrap around to Y = 0, X = 4 and XM0 = 1.
handbook, full pagewidth
byte number
XM0 = 0
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108
XM0 = 1
13 12 11 10 9 8 7 6 5 4 3 2 1 0 136 135 134 133
0 1 2 3 4 5 Y address
930 929 928 927 926 925 924
....
....
6
944 943 942 941 940 939 938 937 936 935 934 933 932 931 119 120 121 122 123 124 125 126 127 0 1 2 3 4
1063 1062 1061 1060 1059 1058 1057 1056 1055 1054 1053 1052 1051 1050 1049 1048 1047 1046 1045 1044 1043 1042 1041 1040 1039
byte order for icon data
7 8
132 131 130
120 119 118 117 116 115 114 113 112 111 110 109 108
icon data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
.. ..
.. ..
X address
MGS678
Fig.11 Sequence of writing data bytes into the RAM with mirrored horizontal addressing (V = 0 and MX = 1).
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13 12 11 10 9 8 7 6 5 4 3 2 1 0
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15.2 OUTPUT ADDRESSING
PCF8535
The output addressing of the RAM is done automatically in accordance with the currently selected multiplex rate. Normally the user would not need to make any alterations to the addressing. There are, however, circumstances pertaining to various connectivity of the device on a glass that would benefit from some in-built functionality. Three modes exist that enable the user to modify the output addressing, namely: 1. MY, mirror the Y axis. This mode effectively flips the display about the X axis, resulting in an upside down display. The effect is observable immediately the bit is modified. This is useful if the device is to be mounted above the display area instead of below. 2. Bottom Row Swap (BRS). This mode swaps the order of the rows on the bottom(1) edge of the chip. This is useful to aide routing to the display when it is not possible to pass tracks under the device; a typical example would be in tape carrier package. This mode is often used in conjunction with TRS. 3. Top Row Swap (TRS). As with BRS, but swaps the order of rows on the top(1) edge of the chip.
7.15.2.1
Mirror Y, MY
As described above, the Y axis is mirrored in the X axis.
handbook, full pagewidth
R0 R1 R2 R3 R4
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28
..
MY = 0
R5 R6 R7 R8
Y axis Mirror
..
R64
... icons ...
Y axis
R55 R56 R57 R58
MY = 1
R59 R60 R61 R62 R63 R64
..
... icons ...
MGS679
Fig.12 Mirror Y behaviour (Mux rate 1 : 65).
(1) The top edge is defined as the edge containing the user interface connections. The bottom edge is the opposing edge.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15.2.2 Bottom Row Swap
PCF8535
Here the order of the row pads is modified. Each block of rows is swapped about its local Y axis.
R16 handbook, full pagewidth
R32
R64
R48
INTERFACE
COLUMNS R15 R0 R33 R47
MGS680
Fig.13 Bottom row swap.
7.15.2.3
Top Row Swap
Here the order of the row pads is modified. Each block of rows is swapped about its local Y axis.
R32 handbook, full pagewidth
R16
R48
R64
INTERFACE
COLUMNS R0 R15 R47 R33
MGS681
Fig.14 Top row swap.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.15.2.4 Output row order
PCF8535
The order in which the rows are activated is a function of bits MY, TRS, BRS and the selected multiplex mode. Tables 9 to 12 give the order in which the rows are activated. In all cases, the RAM is accessed in a linear fashion, starting at zero with a jump to the last row for the icon data. Table 9 Row order for BRS = 0 and TRS = 0 MULTIPLEX MODE 1 : 17 1 : 26 1 : 33 1 : 49 1 : 65 MY = 0 R0 to R15 and R64 R0 to R24 and R64 R0 to R31 and R64 R0 to R47 and R64 R0 to R64 MY = 1 R15 to R0 and R64 R24 to R0 and R64 R31 to R0 and R64 R47 to R0 and R64 R63 to R0 and R64
Table 10 Row order for BRS = 1 and TRS = 0 MULTIPLEX MODE 1 : 17 1 : 26 1 : 33 1 : 49 1 : 65 MY = 0 R15 to R0 and R64 R15 to R0, R16 to R24 and R64 R15 to R0, R16 to R31 and R64 R15 to R0, R16 to R32, R47 to R33 and R64 R15 to R0, R16 to R32, R47 to R33 and R48 to R64 MY = 1 R0 to R15 and R64 R24 to R16, R0 to R15 and R64 R31 to R16, R0 to R15 and R64 R33 to R47, R32 to R16, R0 to R15 and R64 R63 to R48, R33 to R47, R32 to R16, R0 to R15 and R64
Table 11 Row order for BRS = 0 and TRS = 1 MULTIPLEX MODE 1 : 17 1 : 26 1 : 33 1 : 49 1 : 65 MY = 0 R0 to R15 and R48 R0 to R15, R32 to R24 and R48 R0 to R15, R32 to R17 and R48 R0 to R15, R32 to R16, R33 to R47 and R48 R0 to R15, R32 to R16, R33 to R47 and R64 to R48 MY = 1 R15 to R0 and R48 R24 to R32, R15 to R0 and R48 R17 to R32, R15 to R0 and R48 R47 to R33, R16 to R32, R15 to R0 and R48 R49 to R64, R47 to R33, R16 to R32, R15 to R0 and R48
Table 12 Row order for BRS = 1 and TRS = 1 MULTIPLEX MODE 1 : 17 1 : 26 1 : 33 1 : 49 1 : 65 MY = 0 R15 to R0 and R48 R15 to R0, R32 to R24 and R48 R15 to R0, R32 to R17 and R48 R15 to R0, R32 to R16, R47 to R33 and R48 R15 to R0, R32 to R16, R47 to R33 and R64 to R48 MY = 1 R0 to R15 and R48 R0 to R15, R32 to R24 and R48 R0 to R15, R17 to R32 and R48 R0 to R15, R16 to R32, R33 to R47 and R48 R0 to R15, R16 to R32, R33 to R47, R47 to R64 and R48
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.16 Instruction set * Oscillator off * VLCDIN may be disconnected
PCF8535
Data accesses to the PCF8535 can be broken down into two areas, those that define the operating mode of the device and those that fill the display RAM; the distinction being the D/C bit. When the D/C bit is at logic 0, the chip will respond to instructions as defined in Table 16. When the D/C bit is at logic 1, the chip will store data into the RAM. Data may be written to the chip that is independent to the presence of the display clock. There are 4 instruction types. Those which: 1. Define PCF8535 functions such as display configuration, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are the most frequently used. To lessen the MPU program load, automatic incrementing by one of the internal RAM address pointers after each data write is implemented. The instruction set is broken down into several pages, each command page being individually addressed via the H[2:0] bits. 7.16.1 RAM READ/WRITE COMMAND PAGE
* I2C-bus interface accesses are possible * RAM contents are not cleared; RAM data can be written * Register settings remain unchanged. V When V = 0, horizontal addressing is selected. When V = 1, vertical addressing is selected. The behaviour is described in Section 7.15.
7.16.2.3
RAM page
The XM0 bit extends the RAM into a second page. The bit may be considered to be the Most Significant Bit (MSB) of an 8-bit X address. The behaviour is described in Section 7.15.
7.16.2.4
Set Y address
The Y address is used as a pointer to the RAM for RAM writing. The range is 0 to 8. Each bank corresponds to a set of 8 rows, the only exception being bank 8, which contains the icon data and is only 1-bit deep; see Table 13. Table 13 Y address pointer Y[3] 0 0 0 0 0 0 0 0 1 Y[2] 0 0 0 0 1 1 1 1 0 Y[1] 0 0 1 1 0 0 1 1 0 Y[0] 0 1 0 1 0 1 0 1 0 BANK bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 (icons) ROWS R0 to R7 R8 to R15 R16 to R23 R24 to R31 R32 to R39 R40 to R47 R48 to R55 R56 to R63 R64
This page is special in that it is accessible independently of the H bits. This page is mainly used as a stepping stone to other pages. Sending the `Default H[2:0]' command will cause an immediate step to the `Function and RAM command page' which will allow the H[2:0] bits to be set. 7.16.2 FUNCTION AND RAM COMMAND PAGE
7.16.2.1
Command page
Setting H[2:0] will move the user immediately to the required command page. Pages not listed should not be accessed as the behaviour is not defined.
7.16.2.2
PD
Function set
When PD = 1, the LCD driver is in power-down mode: * All LCD outputs at VSS
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.16.2.5 Set X address 7.16.3.3 Bias system
PCF8535
The X address is used as a pointer to the RAM for RAM writing. The range of X is 0 to 127 (7FH) and may be extended by the XM0 bit. The combined value of XM0 and X address directly corresponds to the display column number when MX = 0 and corresponds to the inverse display column number when MX = 1; see Table 14. Table 14 X address pointer XM0, X[6:0] 0 1 2 3 : 129 130 131 132 7.16.3 ADDRESSED ADDRESSED COLUMN, MX = 0 COLUMN, MX = 1 C0 C1 C2 C3 : C129 C130 C131 C132 C132 C131 C130 C129 : C3 C2 C1 C0
BS[2:0] sets the bias system; see Section 7.10.
7.16.3.4
Display size
Physically large displays require stronger drivers. Bit IB enables the user to select a stronger driving mode and should be used if suitable display quality can not be achieved with the default setting.
7.16.3.5
Multiplex rate
M[2:0] sets the multiplex rate; see Section 7.9. 7.16.4 HV-GEN COMMAND PAGE
7.16.4.1
PRS
HV-gen control
Programmable charge pump range select. This bit defines whether the programmed voltage for VOP is in the low or the high range. The behaviour of this bit is further described in Section 7.13. HVE High voltage generator enable. When set to logic 0, the charge pump is disabled. When set to logic 1, the charge pump is enabled.
DISPLAY SETTING COMMAND PAGE
7.16.3.1
Display control
The D and E bits set the display mode as given in Table 15. Table 15 Display control D 0 1 0 1 E 0 0 1 1 MODE display blank normal mode all display segments on inverse video
7.16.4.2
HV-gen stages
S[1:0] set the multiplication factor of the charge pump ranging from times 2 to times 5. The behaviour of these bits is further described in Section 7.14.
7.16.4.3
Temperature coefficients
TC[2:0] set the required temperature coefficient. The behaviour of these bits is further described in Section 7.12.
7.16.3.2
External display control
7.16.4.4
Temperature measurement control
Mirror X and mirror Y have the effect of flipping the display left to right or top to bottom respectively. MX works by changing the order data that is written into the RAM. As such, the effects of toggling MX will only be seen after data is written into the RAM. MY works by reversing the order that column data is accessed relative to the row outputs. The effect of toggling MY will be seen immediately. The behaviour of both of these bits is further described in Section 7.15.
The SM bit is used to initiate a temperature measurement. The SM bit is automatically cleared at the end of the measurement. The behaviour of this bit is further described in Section 7.11.
7.16.4.5
VLCD control
VOP[6:0] sets the required operating voltage for the display.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.16.5 SPECIAL FEATURE COMMAND PAGE
PCF8535
When using an external clock and disabling it during power-down mode will further reduce the standby current. If it is not possible to disable it externally then it is worth noting that by selecting the internal clock, which is disabled during power-down mode, the same effect may be achieved.
7.16.5.1
DM
State control
Direct mode allows VLCDOUT to be sourced directly from VDD2. This may be useful in systems where VDD is to be used for VLCD. DOF Display off will turn off all internal analog circuitry that is not required for temperature measurement. As a consequence the display will be turned off. This mode is only required if temperature measurements are required whilst in power-down mode.
7.16.5.3
COG/TCP
The chip may be mounted on either a glass, foil or tape carrier package. For these applications, different organizations of the row pads are required to negate the necessity of routing under the device. The TRS and BRS allow for this swapping. The behaviour of both of these bits is further described in Section 7.15.
7.16.5.2
Oscillator setting
The internal oscillator may be disabled and the source clock for the display derived from the OSC pad. It is important to remember that LCDs are damaged by DC voltages and that the clock, whether derived internally or externally, should never be disabled whilst the display is active. The internal oscillator is switched off during power-down mode. 7.16.6 INSTRUCTION SET
Table 16 Instruction set INSTRUCTION D/C R/W(1) I2C-BUS COMMAND BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 H[2:0] = XXX; RAM read/write command page Write data Read status NOP Default H[2:0] 1 0 0 0 0 1 0 0 D7 D7 0 0 D6 D6 0 0 D5 D5 0 0 D4 D4 0 0 D3 D3 0 0 D2 D2 0 0 D1 D1 0 0 D0 D0 0 1 writes data to display RAM returns result of temperature measurement no operation jump to H[2:0] = 111 I2C-BUS COMMANDS
H[2:0] = 111; function and RAM command page Command page Function set RAM page Set Y address of RAM Set X address of RAM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 X6 0 0 1 0 X5 0 1 0 0 X4 1 0 0 Y3 X3 H2 PD XM0 Y2 X2 H1 V 0 Y1 X1 H0 0 0 Y0 X0 select command page power-down control, data entry mode set RAM page for X address sets Y address of RAM 0Y8 sets X address of RAM 0 X 127
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
I2C-BUS COMMAND BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 H[2:0] = 110; display setting command page Display control External display control Bias system Display size Multiplex rate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 MX BS2 IB M2 1 0 TC2 0 D MY BS1 0 M1 E 0 BS0 0 M0
PCF8535
INSTRUCTION
D/C
R/W(1)
I2C-BUS COMMANDS
sets display mode mirror X, mirror Y set bias system set current for bias system set multiplex rate
H[2:0] = 101; HV-gen command page HV-gen control HV-gen stages Temperature coefficients Temperature measurement control VLCD control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 PRS HVE VLCD range, enable/disable HV-gen S1 TC1 0 S0 TC0 SM # of HV-gen voltage multiplication set temperature coefficient start temperature measurement
0
0
1
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register 0 VLCD 127 0 0 1 0 0 0 0 0 0 1 1 0 DOF DM EC 0 0 0 display off, direct mode enable/disable the internal oscillator top row swap, bottom row swap
H[2:0] = 011; special feature command page State control Oscillator setting COG/TCP Note 1. R/W is set in the slave address. 0 0 0 0 0 0 0 0 0
TRS BRS 0
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
Table 17 Description of the symbols used in Table 16 BIT PD V HVE PRS SM MX MY TRS BRS EC DM(1) DOF(1) IB Note 1. Conditional on other bits. Table 18 Priority behaviour of bits PD, DOF, HVE and DM; note 1 PD 1 0 0 0 0 Note 1. X = don't care state. DOF X 1 0 0 0 HVE X X 1 0 0 DM X X X 1 0 MODE chip is in power-down mode as defined under PD chip is active horizontal addressing voltage multiplier disabled VLCD programming range LOW no measurement no X mirror no Y mirror top row swap inactive bottom row swap inactive internal oscillator enabled; OSC pad ignored direct mode disabled display off mode disabled low current mode for smaller displays 0 vertical addressing voltage multiplier enabled VLCD programming range HIGH start measurement mirror X mirror Y top row swap active bottom row swap active 1 chip is in power-down mode
PCF8535
internal oscillator disabled; OSC pad enabled for input direct mode enabled display off mode enabled high current mode for larger displays
all analog blocks except those required for temperature measurement are off chip is active and using the internal VLCD generator chip is active and using VDD as VLCD chip is active and using an external VLCD generator attached to VLCDIN
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.17 7.17.1 I2C-bus interface CHARACTERISTICS OF THE I2C-BUS
PCF8535
* Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
7.17.1.1
Bit transfer
7.17.1.4
Acknowledge
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.15.
7.17.1.2
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.16.
7.17.1.3
System configuration
The system configuration is illustrated in Fig.17. * Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer
Each byte of 8 bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Fig.18.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.15 Bit transfer.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.16 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.17 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.18 Acknowledgement on the I2C-bus.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
7.17.2 I2C-BUS PROTOCOL
PCF8535
After the acknowledgement cycle of a write, a control byte follows which defines the destination for the forthcoming data byte and the mode for subsequent bytes. For a read, the PCF8535 will immediately start to output the requested data until a NOT acknowledge is transmitted by the master. The sequence should be terminated by a STOP in the event that no further access is required for the time being, or by a RE-START, should further access be required. For ease of operation a continuation bit, Co, has been included. This bit allows the user to set-up the chip configuration and transmit RAM data in one access. A data selection bit, D/C, defines the destination for data. These bits are contained in the control byte. DB5 to DB0 should be set to logic 0. These bits are reserved for future expansion.
The PCF8535 is a slave receiver/transmitter. If data is to be read from the device the SDAOUT pad must be connected, otherwise SDAOUT is unused. Before any data is transmitted on the I2C-bus, the device which should respond is addressed. Four slave addresses, 0111100, 0111101, 0111110 and 0111111 are reserved for the PCF8535. The Least Significant Bits (LSBs) of the slave address is set by connecting SA1 and SA0 to either logic 0 (VSS) or logic 1 (VDD). A sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer.
Table 19 Co and D/C definitions BIT Co 0/1 0 1 D/C 0 1 0 1 0 1 R/W n.a. ACTION last control byte to be sent: only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition another control byte will follow the data byte unless a STOP or RE-START condition is received data byte will be decoded and used to set up the device data byte will return the contents of the currently selected status register data byte will be stored in the display RAM no provision for RAM read back is provided
An example of a write access is given in Fig.19. Here, multiple instruction data is sent, followed by multiple display bytes. An example of a read access is given in Fig.20.
handbook, full pagewidth
acknowledgement from PCF8535
acknowledgement from PCF8535
acknowledgement from PCF8535
acknowledgement from PCF8535
acknowledgement from PCF8535
SS S 0 1 1 1 1 A A 0 A 1 D/C 10 slave address
control byte
A
data byte
A 0 D/C
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
MGS682
AP
R/W
Co
2n 0 bytes
Co
1 byte
update data pointer
Fig.19 Master transmits to slave receiver; write mode.
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Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, full pagewidth
acknowledgement from PCF8535
NOT acknowledgement from master
SS S 0 1 1 1 1 A A 1 A temp. read out value A P 10 slave address STOP condition
MGS683
R/W
Fig.20 Master reads a slaves' status register.
8 LIMITING VALUES (PROVISIONAL) In accordance with the Absolute Maximum Rating System (IEC 134); notes 1, 2 and 3. SYMBOL VDD IDD VLCD ILCD ISS VI/VO II IO Ptot P/out Tamb Tstg Tj(max) Notes 1. Stresses above these values listed may cause permanent damage to the device. 2. Parameters are valid over the operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. 3. VSS = 0 V. 9 HANDLING supply voltage supply current LCD supply voltage LCD supply current negative supply current input/output voltage (any input/output) DC input current DC output current total power dissipation per package power dissipation per output ambient temperature storage temperature maximum junction temperature PARAMETER MIN. -0.5 -50 -0.5 -50 -50 -0.5 -10 -10 - - -40 -65 - MAX. +7.0 +50 +17.0 +50 +50 VDD + 0.5 +10 +10 300 30 +85 +150 150 V mA V mA mA V mA mA mW mW C C C UNIT
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices").
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Objective specification
65 x 133 pixel matrix driver
10 DC CHARACTERISTICS VDD = 4.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 16.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VLCDIN LCD supply voltage Mux mode 1 : 65 Mux mode 1 : 49 Mux mode 1 : 34 Mux mode 1 : 26 Mux mode 1 : 17 ILCDIN VLCDOUT VDD1, VDD2, VDD3 IDD LCD supply current generated supply voltage supply voltage normal mode; notes 1 and 2 normal mode; notes 1 and 4 LCD voltage generator enabled 8.0 8.0 - - - - - - 4.5 - - - - - 40 18 - - PARAMETER CONDITIONS MIN. TYP.
PCF8535
MAX.
UNIT
16.0 16.0 16.0 16.0 16.0 90 40 16.0 5.5
V V V V V A A V V
supply current
power-down mode; notes 1, 3 and 5 display off mode; notes 1 and 5 normal mode; notes 1 and 6 normal mode; notes 1 and 2
- - - - VSS
2 - 160 40 - - - - - 0 0 27
10 - 350 90
A A A A
Logic VIL VIH IOL IL Ro(col) Ro(row) Vbias(col) Vbias(row) tcut Notes 1. LCD outputs are open-circuit, inputs at VDD or VSS, bus inactive, fOSC = typical internal oscillator frequency. 2. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = 12.0 V and external VLCD. 3. Power-down mode. During power-down all static currents are switched off. 4. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = VDD2 and external VLCD. 5. Internal VLCD generation or external VLCD. 6. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = 12.0 V and voltage multiplier = 3VDD. 7. ILCD = 10 A. Outputs tested one at a time. 1999 Aug 24 33 LOW-level input voltage HIGH-level input voltage LOW-level output current (SDA) leakage current VOL = 0.4 V; VDD = 5 V VI = VDD or VSS 0.3VDD V VDD - +1 10 3.0 +100 +100 - V mA A k k mV mV C 0.7VDD - 3.0 -1 - - -100 -100 Tamb = -20 to +70 C -
Column and row outputs column output resistance C0 to C132 VLCD = 12 V; note 7 row output resistance R0 to R33 bias tolerance C0 to C132 bias tolerance R0 to R64 cut point temperature VLCD = 12 V; note 7
Temperature coefficient
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
11 AC CHARACTERISTICS VDD = 4.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 16.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL ffr(LCD) fclk(ext) tW(RESL) tW(RESH) tSU;RESL tR(op) fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA tSU;STO tSP tBUF Notes 1. VDD1 to VDD3 = 5 V. PARAMETER LCD frame frequency (internal clock) external clock frequency reset LOW pulse width reset HIGH pulse width reset LOW pulse set-up time after power-on end of reset pulse to interface being operational notes 1 and 2 see Table 20 CONDITIONS 48 120 1 5 - - 0 1.3 0.6 100 0 note 4 note 4 MIN. - - - - - - - - - - TYP. 80
PCF8535
MAX. 165 410 - - 30 3
UNIT Hz kHz s s s s kHz s s ns s ns ns pF s s s ns s
Serial-bus interface; note 3 SCL clock frequency SCL clock LOW period SCL clock HIGH period data set-up time data hold time SCL, SDA rise time SCL, SDA fall time capacitive load represented by each bus line set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus bus free time between a STOP and START condition 400 - - - 0.9 300 300 400 - - - 50 -
20 + 0.1Cb - 20 + 0.1Cb - - 0.6 0.6 0.6 - 1.3 - - - - - -
2. Decoupling capacitor VLCD and VSS = 100 nF (higher capacitor size increases tSU;RESL and higher VDD1 to VDD3 reduces tSU;RESL). 3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 4. Cb = total capacitance of one bus line in pF.
1999 Aug 24
34
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.21 I2C-bus timing diagram.
Table 20 External clock frequency MUX MODE 1 : 65 1 : 48 1 : 33 1 : 26 1 : 17 DIVISION RATIO 3168 3136 2720 2592 2592 EXTERNAL CLOCK FREQUENCY FOR AN 80 Hz FRAME FREQUENCY (DIVISION RATIO x 80 Hz) 253 kHz 251 kHz 218 kHz 207 kHz 207 kHz
1999 Aug 24
35
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
12 RESET TIMING
PCF8535
handbook, full pagewidth
VDD t W(RESL) RES t W(RESH) t W(RESL)
VDD t SU;RESL RES t W(RESL) t W(RESH) t W(RESL)
RES t R(op) SDA, SCL
MGS684
Fig.22 Reset timing.
1999 Aug 24
36
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
13 APPLICATION INFORMATION Table 21 Programming example for PCF8535 STEP 1 2 3 4 SERIAL BUS BYTE START condition DISPLAY(1) BLANK start
PCF8535
OPERATION slave address, R/W = 0 control byte, Co = 0, D/C = 0 H[2:0] independent command; select function and RAM command page H[1:0] = 111 function and RAM command page; PD = 0, V = 0 function and RAM command page; select display setting command page H[1:0] = 110 display setting command page; set bias system to 1/9BS[2:0] = 010 display setting command page; set normal mode (D = 1, E = 0) select Mux rate 1 : 65 H[2:0] independent command; select function and RAM command page H[1:0] = 111 function and RAM command page; select Hv-gen command page H[1:0] = 101 Hv-gen command page; select voltage multiplication factor 3 S[1:0] = 01 Hv-gen command page; select temperature coefficient 2 TC[2:0] = 010 Hv-gen command page; set VLCD = 12.02 V; VOP[6:0] = 0101000 Hv-gen command page; select high VLCD programming range (PRS = 1), voltage multiplier on (HVE = 1) repeat start slave address, R/W = 0 control byte, Co = 0, D/C = 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 1 1 1 1 SA1 SA0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 0 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 1 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 1 1 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 1 0 0 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 0 1 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 1 0 0 0 0 1 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 0 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 1 1 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 1 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 1 0 0 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 1 0 1 0 1 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 0 0 0 0 1 1 1
5 6
7 8 9 10
11
12
13
14
15
16 17 18
START condition
BLANK
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 1 1 1 1 SA1 SA0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK 0 1 0 0 0 0 0 0
1999 Aug 24
37
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
DISPLAY(1)
PCF8535
STEP 19
SERIAL BUS BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 1 1
OPERATION data write; Y, X are initialized to logic 0 by default, so they are not set here
MGS405
20
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 1
data write
MGS406
21
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 1 1
data write
MGS407
22
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0
data write
MGS408
23
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 1 1
data write
MGS409
24
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 0
data write
MGS410
25
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 1 1
data write, last data, stop transmission
MGS411
26 27
START condition DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 1 1 SA1 SA0 0
repeat start slave address, R/W = 0
MGS411
1999 Aug 24
38
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
DISPLAY(1)
PCF8535
STEP 28
SERIAL BUS BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
OPERATION control byte, Co = 1, D/C = 0
MGS411
29
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1
H[1:0] independent command; select function and RAM command page H[1:0] = 111
MGS411
30
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
control byte, Co = 1, D/C = 0
MGS411
31
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 0
function and RAM command page; select display setting command page H[1:0] = 110
MGS411
32
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
control byte, Co = 1, D/C = 0
MGS411
33
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 1
display control; set inverse video mode (D = 1, E = 1)
MGS412
34
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
control byte, Co = 1, D/C = 0
MGS412
35
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
set X address of RAM; set address to `0000000'
MGS412
1999 Aug 24
39
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
DISPLAY(1)
PCF8535
STEP 36
SERIAL BUS BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 0 0 0 0
OPERATION control byte, Co = 0, D/C = 1
MGS412
37
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0
data write
MGS414
38
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0
data write
MGS685
39
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0
data write
MGS686
40 Note
STOP condition
end of transfer
1. Assumes the display RAM was previously empty. The pinning of the PCF8535 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 65 x 133 pixels.
1999 Aug 24
40
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, full pagewidth
DISPLAY 65 x 133 PIXELS
33
133
32
PCF8535
R I/O
Rsupply
Rcommon
3 VSS1, I/O VDD1 to VDD3 VSS2
Cext
VLCD
MGS687
Fig.23 Application diagram (COG).
The required minimum value for the external capacitors in an application with the PCF8535 are: Cext for VLCD, VSS1 and VSS2 = 100 nF (min.) (recommended 470 nF to 1 F); Cext for VDD1 to VDD3, VSS1 and VSS2 = 470 nF (recommended capacitor larger than the capacitor for VLCD, VSS1 and VSS2). Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections. Maximum values for supply tracks (Rsupply) are 120 . Maximum values for the common resistance to the source, (Rcommon) are 120 . Higher track resistance reduces performance and increases current consumption. Three I/O lines are required for the COG module; SDA, SCL and RES (optional). Other signals may be fixed on the module to appropriate levels. RI/O should also be minimized. In particular, if the I2C-bus acknowledge or temperature read back is required, the RI/O for the SDA line must be carefully considered in conjunction with the value of the external pull-up resistor.
1999 Aug 24
41
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
14 BONDING PAD LOCATIONS Table 22 Bonding pad locations All x and y coordinates are referenced to the centre of the chip (dimensions in m; see Fig.27). SYMBOL dummy R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 1999 Aug 24 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 bump/align 1 2 PAD x -1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 y -6156 -6081 -5985 -5915 -5845 -5775 -5705 -5635 -5565 -5495 -5425 -5355 -5285 -5215 -5145 -5075 -5005 -4935 -4725 -4655 -4585 -4515 -4445 -4305 -4235 -4165 -4095 -4025 -3955 -3885 -3815 -3745 -3675 -3605 -3535 -3465 -3395 42
PCF8535
SYMBOL C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
PAD
x +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050
y -3325 -3255 -3185 -3115 -3045 -2975 -2905 -2835 -2765 -2695 -2625 -2555 -2485 -2415 -2345 -2275 -2205 -2135 -1995 -1925 -1855 -1785 -1715 -1645 -1575 -1505 -1435 -1365 -1295 -1225 -1155 -1085 -1015 -945 -875 -805 -735 -665 -595 -525 -455
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
SYMBOL C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 1999 Aug 24 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
PAD
x +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 -385 -315 -245 -175 -105 -35 +35 +105 +175 +315 +385 +455 +525 +595 +665 +735 +805 +875 +945
y
SYMBOL C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 R47 R46 R45 R44 R43 R42 R41 R40 R39 43 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
PAD
x +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050 +1050
y +2625 +2695 +2765 +2835 +2905 +2975 +3045 +3115 +3185 +3255 +3325 +3395 +3465 +3535 +3605 +3675 +3745 +3815 +3885 +3955 +4025 +4095 +4165 +4235 +4305 +4375 +4445 +4515 +4585 +4655 +4725 +4795 +5005 +5075 +5145 +5215 +5285 +5355 +5425 +5495 +5565
+1015 +1085 +1155 +1225 +1295 +1365 +1435 +1505 +1575 +1645 +1715 +1785 +1855 +1925 +1995 +2065 +2135 +2205 +2275 +2345 +2415 +2485
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
SYMBOL R38 R37 R36 R35 R34 R33 dummy R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 dummy dummy dummy OSC VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT 1999 Aug 24 161 162 163 164 165 166 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201
PAD
x +1050 +1050 +1050 +1050 +1050 +1050 +1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050
y +5635 +5705 +5775 +5845 +5915 +5985 +6081 +6094 +5954 +5884 +5814 +5744 +5674 +5604 +5534 +5464 +5394 +5324 +5254 +5184 +5114 +5044 +4974 +4904 +4834 +4414 +4274 +3996 +3574 +3154 +2874 +2804 +2734 +2664 +2594 +2524 +2384 +2314 +2244 +2174 +2104 44
SYMBOL VLCDOUT VLCDOUT VLCDSENCE dummy dummy RES T3 T2 T1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 VDD3 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 dummy SDA SDA SDAOUT SA1 SA0 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242
PAD
x -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050
y +2034 +1964 +1894 +1544 +1264 +914 +704 +494 +284 +144 +74 +4 -66 -136 -206 -276 -346 -416 -486 -556 -626 -696 -766 -836 -906 -976 -1046 -1186 -1466 -1536 -1886 -2166 -2376 -2586 -2656 -2726 -2796 -2866 -2936 -3006 -3076
bump/align 2 167
bump/align 3 186
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
Table 23 Alignment marks MARKS Alignment mark 1 Alignment mark 2 Alignment mark 3 Alignment mark 4 x -1045 -1045 +1045 +1045
PCF8535
SYMBOL VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T5 T4 dummy SCL SCL R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 243 244 245 246 247 248 249 250 251 252 253 254 255 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273
PAD
x -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050 -1050
y -3146 -3216 -3286 -3356 -3426 -3496 -3566 -3636 -3846 -4056 -4126 -4406 -4476 -4605 -4826 -4896 -4966 -5036 -5106 -5176 -5246 -5316 -5386 -5456 -5526 -5596 -5666 -5736 -5806 -5876 -5946
y -4720 +4620 +6196 -6196 -6081 +6081 +4414 -4605 -6330 +6330
Dummy bump/alignment +1050 mark 1 Dummy bump/alignment +1050 mark 2 Dummy bump/alignment -1050 mark 3 Dummy bump/alignment -1050 mark 4 Bottom left Top right Table 24 Bonding pads PAD Pad pitch Pad size; Al CBB opening Bump dimensions Wafer thickness (including bumps) SIZE minimum 70 62 x 100 36 x 76 -1180 +1180
bump/align 4 256
UNIT m m m m m
50 x 90 x 17.5 ( 5) maximum 381
1999 Aug 24
45
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, halfpage
handbook, halfpage
y centre
100 m
y centre
80 m
x centre
MGS688
x centre
MGS689
Fig.24 Shape of alignment mark.
Fig.25 Shape of dummy bump/alignment mark.
handbook, halfpage
12.66 mm
2.36 mm
PCF8535
pitch
MGS690
Fig.26 Bonding pads.
1999 Aug 24
46
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
PCF8535
handbook, full pagewidth
R48 .
. . . . .
R33 .
. . . . .
R64
R47 C132 .
. .
VLCDIN VLCDOUT VLCDSENSE
RES T3 T2 T1 y VDD2 VDD3 VDD1 0, 0 x
SDA SDAOUT SA1 SA0 VSS2 VSS1 T5 T4 SCL R32 .
PC8535
OSC
. . .
C0 R15 .
. . . . .
. . . . .
R16 PAD ONE Dummy bump Alignment mark The position of the bonding pads is not to scale.
MGS693
R0
Fig.27 Bonding pad location (viewed from bump side).
1999 Aug 24
47
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
15 DEVICE PROTECTION DIAGRAM
PCF8535
handbook, full pagewidth
PADS 223 to 228
PADS 211 to 218
PADS 219 to 222
VDD1
PADS 243 to 250
VDD2
VDD3
VSS1
VSS1
PADS 235 to 242
VSS1
VSS2
PADS PADS 197 to 203
VSS2
PADS 191 to 196, 204
VLCDOUT VLCDIN, VLCDSENSE VSS1
VSS1
VSS1
VDD1
PADS 254, 255, 230 to 232
VLCDIN
PADS 3 to 166, 169 to 185, 257 to 273
SCL, SDA, SDAOUT
VSS1
VSS1
VDD1
PADS 190, 233, 234, 252, 251, 207
VDD1
PADS 208 to 210
OSC, SA0, SA1, T4, T5, RES
T1, T2, T3
VSS1
MGS672
VSS1
Fig.28 Device diode protection diagram.
1999 Aug 24
48
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
16 TRAY INFORMATION
PCF8535
handbook, full pagewidth
x
A
C
y
D
B F
E
MGS691
The dimensions are given in Table 25.
Fig.29 Tray details.
Table 25 Dimensions DIM. A B C
handbook, halfpage
DESCRIPTION pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets in x direction number of pockets in y direction
VALUE 14.88 mm 4.06 mm 12.76 mm 2.46 mm 50.8 mm 50.8 mm 3 11
D E F
PC8535-1
x y
MGS692
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.30 Tray alignment.
1999 Aug 24
49
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8535
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
20 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Aug 24
50
Philips Semiconductors
Objective specification
65 x 133 pixel matrix driver
NOTES
PCF8535
1999 Aug 24
51
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/01/pp52
Date of release: 1999
Aug 24
Document order number:
9397 750 06201

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